Additional Credit Course on Design and Simulation of ICs, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

After the completion of the course, the students of III year EEE were able to:

• Draw a flow diagram of the entire design flow and explore the entire ASIC design flow process

• Identify the distinction between Digital IC design, verification, and implementation

• Recognize the different stages of front-end design and verification

• Demonstrate the SystemVerilog HDL for design and verification

• Recognize the different stages of design implementation

• Create, verify, and implement a system-level design with a simple architecture

• Identify the challenges of scaling, costs, and physical attributes, as well as low power and area constraints before tapeout

• Identify the different processes in the semiconductor industry used to handle the above realistic challenges