The program is planned for II year students (31 students) of ECE A and B who are having basic knowledge in digital electronics. It was conducted from 03.06.24 to 04.06.24. The resource person started the session with basic concepts of Full and semi custom IC design flow.
Then Verilog HDL basic commands are discussed. Simple programs are written using HDL and simulation outputs are verified. The tools in cadence for synthesis are explained through examples.At the end of day 1 , students are well versed in RTL analysis and synthesis of combinational circuits.
On 04.06.24, the resource person demonstrated the sequential circuits design and Finite State Machine controller design using examples. In the second session, physical implementation using Innovus tool is discussed which includes floor planning, power planning, placement and routing. The students are able to obtain GDSII generation at the end of the program.
The coordinators Dr.B.Jaishankar and Dr.J.Muralidharan conducted the assessment of this program through quiz prepared by the resource person. The feedback about the program is collected from the students for further analysis.
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