Two day Workshop "System Verilog", KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

The department of Electronics and Communication Engineering, in association with the student's association SPARTRANZ, organizes a two-day hands-on training on “Verilog Programming” between 24.10.2025 and 25.10.2025 at the VLSI laboratory. Mr.Krishna Prabhu and Miss. Pallavika Sigamasetti will handle the session. On day 1, 24.10.2025, discussed the following topics under Digital Electronics and VLSI domain.

·        Overview of HDL

·        System Verilog: Introduction

·        System Verilog: Variables, Structures, Unions, Task and function

·        Experiment: Simple combinational circuit using System Verilog

The resource person discussed the design flow of ASICs (Application Specifications Integrated Circuits) and their function in VLSI design on day two, 25.10.2025. After talking about the differences in features between ASIC and FPGA. After discussed about ASIC and FPGA the following topics are covered

·       System Verilog: ATM implementation (Code & test bench)

·       ATM: Transmitter and Receiver, Data abstraction and interface encapsulation

·       Hands on experiment ATM – Code & Test Bench

At the end of the session, students were able to:

1.   Understand the concept, need, and role of Hardware Description Languages (HDLs) in   digital system design.

2.   Describe the key features and advantages of System Verilog over traditional Verilog HDL 

3. Implement tasks and functions for modular and reusable code development.

4. Apply procedural blocks effectively using System Verilog constructs.

5. Design a simplified ATM functional model using SystemVerilog modules.

6. Apply data abstraction techniques to simplify module interactions.

7. Develop and simulate a complete ATM system integrating transmitter, receiver, and

    control modules