ONE-DAY WORKSHOP ON ANNA UNIVERSITY (EC3561 – VLSI LABORATORY) EXPERIMENTS USING CADENCE EDA TOOLS, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

The Department of Electronics and Communication Engineering, KPR Institute of Engineering and Technology organized a hands-on technical training program on Design and Simulate CMOS Basic Gates and Flip Flops. The resource person Mr. Soma Shekhar H, Product Manager – Cadence EASI discussed the latest technology in VLSI domain and showcased the job opportunities for VLSI Design engineers in the globe. He also added the internship opportunities provided by Entuple Technologies for both UG and PG graduates. Then the session was handled by Dr. Muralidharan J, Associate Professor, Department of ECE, KPR Institute of Engineering and Technology. During the session resource person discussed on the evolution and importance of the CMOS technology and EDA tools. Then elaborated the operations of all the logic gates and flip flops with symbols and truth table. The next resource person is Mr. Navaneethakrishnan V, Sr. Application Engineer (AE), Entuple Technologies Pvt. Ltd. explained the intricate journey of transforming a Register Transfer Level (RTL) description into the final Graphic Data System (GDS) file in the world of VLSI (Very Large Scale Integration) chip design. The faculty members from various institutions participated in the workshop event.