VLSI DESIGN FLOW USING CADENCE TOOL, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

The event's outcome is that the participants can understand the VLSI Design flow using the Cadence tool. Also, the participants had hands-on experience in circuit design and analysis.

The two-day workshop on VLSI Design Flow using Cadence Tools aimed to provide participants with in-depth knowledge and hands-on experience in the field of Very Large Scale Integration (VLSI) design. The workshop focused on utilizing Cadence tools throughout the design flow, covering key stages such as specification, design, verification, synthesis, and layout.

The workshop agenda included the following key sessions on Introduction to Semi-Custom IC Design Flow, Functional Verification using Incisive, RTL Synthesis using Genus Synthesis Solution, Physical Implementation using Innovus that includes Floor Planning, Power Planning, Placement, CTS, Routing, Verification checks like DRC, connectivity, Parasitic Extraction, Generation of GDSII.

Introduction to Full Custom IC Design Flow, Capture using Virtuoso Schematic Editor, Symbol Creation, Testbench Creation using Virtuoso Symbol Editor,

Functional Simulation using Spectre, Layout Design using Virtuoso Layout Suite, Physical Verification which includes DRC & LVS, Parasitic Extraction using Quantus, Post Layout Simulation, Generation of GDSII

The workshop began with an insightful introduction to VLSI design and an overview of the Cadence tool suite. The resource person is an industry expert Mr. Priyanshu Datta, Entuple Technologies with extensive experience, provided valuable insights into the latest trends and best practices in the field. Participants actively engaged in hands-on sessions using Cadence tools for schematic entry, simulation, synthesis, and layout. The workshop included showcasing successful applications of VLSI design using Cadence tools.

The Workshop on VLSI Design Flow using Cadence Tools proved to be a valuable learning experience for participants, providing them with practical skills, industry insights, and a deeper understanding of the VLSI design process. The event successfully fostered collaboration and networking within the VLSI community.